In design optimization and implementation of discrete capacitors for power decoupling in electronic appliances and systems, series resistance to a discrete or embedded decoupling capacitor is typically provided by using an annular ring of resistive material printed or formed around the capture pad of vias connected to the discrete decoupling capacitor. The decoupling capacitor is thus connected through a series resistor to the power planes. This design has a number of drawbacks, including:                The gap between the vias interconnecting the decoupling capacitor is determined by the diameter of the annular ring, thereby increasing via pitch for the decoupling capacitor interconnection.        The gap between the vias interconnecting the decoupling capacitor is determined by the diameter of the annular ring, limiting the via coupling effect and thereby actually increasing the effective inductance of the decoupling capacitor interconnection and degrading the power decoupling performance.        The series resistance between the decoupling capacitor and power planes is provided through a lateral interconnection that inhibits direct interconnection between active devices and decoupling capacitor, resulting in additional loop inductance between the decoupling capacitor and active device, and also degrading signal routability.        The series resistance employed using resistive materials on the power planes affects the effective resistance at dc or low frequency for high current path, degrading electrical performance, especially for high power devices        The series resistance employed using resistive materials on the power planes also introduces additional thermal resistance due to intrinsic thermal properties of resistive materials. Power planes are inherently lateral thermal conducting paths that provide heat dissipation from active devices.        
A need therefore exists for a decoupling capacitor interconnection design and method that addresses one or more of the above mentioned drawbacks.